1. Field of the Invention
The present invention relates generally to improvement on bias supply by being equipped with a bias bypass line independent from a signal line in a distributed high frequency circuit in which outputs of a plurality of transistors are connected in parallel to each other, more particularly, to a distributed high frequency circuit amplifying a microwave or millimeter wave signal, or mixing a local oscillation wave into an RF (Radio Frequency) or IF (Intermediate Frequency) signal.
2. Description of the Related Art
FIG. 7 shows a transmitter 10 of a base station for a portable telephone.
An IF signal and an local oscillation (Local Oscillator) signal are provided to a mixer 11 to generate an RF (Radio Frequency) signal, which is amplified to a large signal by a low noise amplifier 12 and a high-power amplifiers 13 and 14 connection in cascade, and in turn provided to an antenna not shown. Since amplifiers of such a transmitter 10 are required to have large current driving ability, the amplifier has amplifying transistors connected in parallel.
FIG. 8 shows such a prior art distributed high frequency amplifier 20W.
A high frequency signal provided to an input IN is equally distributed through a capacitor 21 and a power splitter circuit 22 to the gates of transistors 23A and 23B connected in parallel. The power splitter 22 also plays a role as an impedance matching circuit. In order to supply biases to the gates of the transistors 23A and 23B such that a high frequency signal does not leak to a gate bias input G, a resistor 24 is connected between the gate bias input G and the gate of the transistor 23A. A resistor 25 for bias adjustment is connected between the gate bias input G and ground. A bias is provided to the gate of the transistor 23B through the resistor 24 and a line of the power splitter circuit 22. The resistance value of the resistor 24 is determined such that a large variation of the bias does not arise by leaking through the resistor 24 when a signal with a large amplitude is propagating for the gates of the transistors 23A and 23B. A resistor 26 connected between the gates of the transistors 23A and 23B works to stabilize signals provided to the gates of the transistors 23A and 23B in a case where these signals are unbalanced, and each has the resistance value of several ohms. The capacitor 21 is employed to block the gate bias to leak out on the input IN side.
The drains of the transistors 23A and 23B are connected through a power superimposition circuit 27W and a capacitor 28 to an output OUT. The power superimposition circuit 27W also plays a role as an impedance matching circuit. In order to apply a bias voltage to the drains of the transistors 23A and 23B, a drain bias transmission line 29WB is connected between a drain bias input terminal DB and the output of the power superimposition circuit 27W and a capacitor 30B is connected to an end of the drain bias transmission line 29WB. The length of the drain bias transmission line 29WB is xcex/4, where xcex denotes a signal wavelength. The capacitor 30B is used for signal grounding. With the drain bias transmission line 29WB and the capacitor 30B, the impedance of the drain bias transmission line 29WB side measured at a node N0 between the power superimposition circuit 27W and a capacitor 28 is infinite in an ideal case, thereby blocking a signal to flow to the drain bias transmission line 29WB side from the node N0. The capacitor 28 is used to block a drain bias to leak out to the output OUT.
In order to increase the output power of the distributed high frequency amplifier 20W, it is required to increase the drain currents of the transistors 23A and 23B. When the distributed high frequency amplifier 20W is formed in an MMIC (Monolithic Microwave Integrated Circuit), a metal film of a line is thin and sheet resistance thereof is comparatively large, so the line width is required to be wide such that a voltage drop caused by a resistance component is reduced. The line width of the drain bias transmission line 29WB is required to be wide since the drain current for the two transistors 23A and 23B flows therethrough. Further, since the drain current flows through the power superimposition circuit 27W, the width of a current path thereof also has to be wider.
However, since the power superimposition circuit 27W is necessary to work as the matching circuit as well, the line width thereof is limited. Further, the impedance of the drain bias transmission line 29WB side measured at the node N0 is actually finite and a high frequency signal leaking out to the drain bias transmission line 29WB side from the node N0 is proportional to the ratio of the impedance of the configuration from which the drain bias transmission line 29WB is removed measured at the node N0 to the impedance of the drain bias transmission line 29WB side from the node NO. Hence, the position of the node N0 is preferably closer to the drain electrodes of the transistors 23A and 23B each with a relatively small impedance. In other words, since the node N0 is disposed apart from the drain electrodes of the transistors 23A and 23B, a signal is leaked out to the drain bias transmission line 29WB side from the node NO.
FIG. 9 shows a configuration to be able to solve such problems, wherein one ends of drain bias transmission lines 29A and 29B are connected to the drain electrodes of the respective transistors 23A and 23B so as to be close thereto. The other end of the drain bias transmission line 29A is connected to a drain bias input DA, on one hand, and grounded through a capacitor 30A, on the other hand. Likewise, the other end of the drain bias transmission line 29B is connected to the drain bias input terminal DB, on one hand, and grounded through the capacitor 30B, on the other hand.
In such a configuration, since no drain bias current flows through the power superimposition circuit 27, the line width of the power superimposition circuit 27 can be designed freely such that the power superimposition circuit 27 functions sufficiently as a matching circuit. Further, each width of the drain bias transmission lines 29A and 29B can be half that of the drain bias transmission line 29WB of FIG. 8 since the value of drain current flowing through each of the drain bias transmission lines 29A and 29B is half that of the drain bias transmission line 29WB of FIG. 8. Furthermore, signals leaked out into the drain bias transmission lines 29A and 29B from nodes NA and NB can be reduced.
However, since the two drain bias inputs DA and DB are required to be provided on both sides of the circuit, wiring of the drain bias transmission lines between a plurality of distributed amplifiers are complex in a case where the plurality of distributed amplifiers are cascaded as shown in FIG. 7.
FIG. 10 shows a configuration to be able to solve such a problem, wherein the drain bias is only provided from the drain bias input terminal DB. However, the drain current to the transistor 23A flows through the power superimposition circuit 27W; therefore the line width of the power superimposition circuit 27W is necessary to be wider, which disables the line width to be freely designed such that the power superimposition circuit 27W works sufficiently as the matching circuit. Further, it is necessary to flow a drain current into the drain bias transmission line 29WB for the two transistors 23A and 23B, and it is necessary to make the drain load of the transistor 23A be equal to that of the transistor 23B; therefore the line width of the drain bias transmission lines 29WA and 29WB have to be double that of the drain bias transmission lines 29A and 29B of FIG. 9, leading to increase in chip area.
FIG. 11 shows a layout in a case where the circuit of FIG. 10 is formed in an MMIC.
All the parts of FIG. 11 are enclosed in an IC package. An outer frame FR is of an insulator on which the gate bias input G and the drain bias input terminals DB, which are inner leads, are arranged. Inside the outer frame FR, there are disposed an MMIC chip and microchip condensers 31A and 31B for drain bias voltage stabilization not shown in FIG. 10.
Bonding wires are used in connection between input/output pads on the MMIC chip and electrodes outside the MMIC chip. That is, by bonding wires, one electrode (upper surface) of the microchip condenser 31A is connected to the drain bias transmission line 29WA, one electrode of the microchip condenser 31B is connected to the drain bias transmission line 29WB and the drain bias input terminal DB, and a pad connected to the resistor 24 is connected to the gate bias input G. The other electrodes (lower surface) of the microchip condensers 31A and 31B are grounded.
On the MMIC chip, each resistor is made of a TF (thin film) resistor, each capacitor is made of a MIM (metal-insulator-metal) structure, and each line is a microstrip line. The power splitter circuit 22 comprises transmission lines 221 and 222, and capacitors 223, 224 and 225. The power superimposition circuit 27 W comprises transmission lines 271W and 272W, and capacitors 273 and 274. Each of via holes H1 to H9 and HA to HC of FIG. 11 are to connect an electrode on the front surface to a ground plane on the back surface. Each of the transistors 23A and 23B is constructed of two transistors connected in parallel to each other so as to improve the circuit characteristics (an impedance conversion ratio becomes smaller, and an input signal phase difference between the gates of the transistors 23A and 23B becomes smaller) in comparison with a case where each of the transistors 23A and 23B is constructed of only one transistor.
Although the gate bias resistors 24 are connected to an input side line of the power splitter circuit 22, which is different from the resistor 24 in FIG. 10, there is no problem in either case.
Since the line widths of the drain bias transmission lines 29WA and 29WB, and transmission lines 271W and 272W of the power superimposition circuit 27 W are wide, which cause a larger chip area.
FIG. 12 shows a distributed high frequency amplifier 20Z of a configuration to solve such a problem, wherein a drain bias current does not flow into the power superimposition circuit.
In this distributed high frequency amplifier 20Z, drain bias transmission lines 29C and 29D are connected between the drain bias transmission lines 29WA and 29WB, and the node between the drain bias transmission lines 29C and 29D is grounded through a capacitor 30C for signal grounding. Each length of the drain bias transmission lines 29C and 29D is xcex/4 which is equal to that of the drain bias transmission lines 29WA and 29WB. In regard to signals, the impedance values of the drain bias transmission line 29C side measured at the node NA and the drain bias transmission line 29D side measured at the node NB are both infinite in an ideal case, thereby blocking signal leakage. Since the drain current flowing through the drain bias transmission lines 29C and 29D is for the transistor 23A, the line width thereof is half that of the drain bias transmission line 29WB.
However, the total length of the drain bias transmission lines is double that of FIG. 10, and the line width of the drain bias transmission lines 29WA and 29WB are as wide as that in FIG. 10, so a chip area is larger.
Accordingly, it is an object of the present invention to provide a distributed high frequency circuit capable of decreasing a chip area together with reducing the number of direct current bias terminals without degrading circuit characteristics.
In one aspect of the present invention, there is provided a distributed high frequency circuit wherein outputs of first and second transistors are connected in parallel through a signal superimposing transmission line, and first ends of signal blocking lines are connected to outputs of the first and second transistors, respectively, and a bias supply line is connected between the second ends of the first and second signal blocking lines. The distributed high frequency circuit is, for example, an amplifier circuit or balanced mixer.
With this configuration, since a bias is provided to the outputs of the first and second transistors by externally supplying the bias to any point of the bias supply line, it is enough for the bias to be supplied only from a terminal of one side of the circuit; which makes external wiring for supplying the bias simplified even when a plurality of distributed high frequency circuits are cascaded.
Further, an amount short of current into the signal superimposing transmission line has only to be supplemented through the bias supply line, and the main portion of the bias supply line can be straight; therefore, it is enough for a chip area to be a little larger than a configuration in which biases are provided to the outputs of the first and second transistors from both sides of a distributed high frequency circuit. In other words, the widths of the signal superimposing transmission line and signal blocking lines can be narrower than those of the prior art configuration in which the bias is supplied to the outputs of transistors from one side of the distributed high frequency circuit; therefore a chip area can be smaller.
Besides, since the bias supply line is provided, it is not required that a desired bias current is supplied to the signal superimposing transmission line, and therefore the limitation thereof can be removed from the design of the signal superimposing transmission line, resulting in improving circuit characteristics.
Further, since a bias input terminal may be connected to any position of the bias supply line, degree of freedom to select the position increases.
In the above configuration, if the signal blocking line is folded in a first direction and the bias supply line mainly has a straight portion in a second direction perpendicular to the first direction, the bias supply line can be shorter.
In the above described configuration, if the signal superimposing transmission line is also folded in the first direction, the bias supply line can be further shorter, therefore the bias supply line can be further narrower, resulting in further reducing the chip area.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.